library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;

entity PGnetwork is
generic (N : integer);
port (	A	: in   std_logic_vector(N-1 downto 0);
		B	: in   std_logic_vector(N-1 downto 0);
		Cin	: in   std_logic;
		P	: out std_logic_vector(N-1 downto 0);
		G	: out std_logic_vector(N-1 downto 0)
);
end PGnetwork;

architecture Structural of PGnetwork is

component PG is
port (	A:	in   std_logic;
		B:	in   std_logic;
		P:	out std_logic;
		G:	out std_logic
);
end component;

signal g0 : std_logic;
  
begin

PGnet: for i in 0 to N-1 generate
	case0: if i = 0 generate
		PGnet_0: PG port 
		map (	A => A(i),
				B => B(i),
				P => P(i),
				G => g0
			);
		end generate case0;
	caseOthers: if i /= 0 generate
		PGnet_others: PG port
		map (	A => A(i),
				B => B(i),
				P => P(i),
				G => G(i)
			);
		end generate caseOthers;
end generate PGnet;

G(0) <= g0 or (Cin and A(0)) or (Cin and B(0));

end Structural;
